The Ayre Digital Design Platform (DDP) is a fully modular digital processor with 96
kHz, 24-bit capability. It was created to allow our design team to evaluate both circuit
concepts as well as individual circuit elements (e.g., D/A chips, digital filters).
Although this prototype is only intended as an engineering development tool, its sonic
performance already surpasses the current state-of-the-art, even for 44.1 kHz, 16-bit
playback.
The keys to its extraordinary sound quality are found in a near-total freedom from
jitter and Ayre's proprietary fully-discrete differential current-to-voltage (I-V)
converter. To more fully understand the accomplishment of the DDP, let us look at the five
basic building blocks of a digital playback system: the transport mechanism, the
interface, the digital filter, the D/A converter, and the analog circuitry.
The Transport Mechanism
Presently, transports mechanisms are available as complete modules that include all
sub-components (e.g., optics, decoder, controller, motor) needed to extract the digital
data from the digital playback disk. Perhaps the principal concern for sonic performance
in a transport mechanism is freedom from jitter (timing errors).
Surprisingly, even the most inexpensive transport mechanisms have the potential for
virtually jitter-free performance. As data stream is read from the disk, it is stored in a
FIFO (first-in, first-out) memory buffer. Then it is clocked out by the master clock at a
constant rate. A servo loop controls the incoming data rate by varying the disk's
rotational speed as needed to keep the FIFO buffer half-full.
Any timing variations (jitter) in the incoming data stream are absorbed by the FIFO
buffer. To achieve jitter-free performance, it is only necessary to supply the buffer with
a jitter-free master clock signal, a relatively simple task. The difficulty arises when
the transport is housed in a separate enclosure from the following circuitry and connected
with a single cable using either the S/PDIF (Sony/Philips Digital Interface Format) or
AES/EBU (Audio Engineering Society/European Broadcast Union) format.
Interface
The near-universal single-cable interface formats specify that the master clock be
embedded in the digital data stream via bi-phase encoding. The master clock is then
separated from the various digital data by the receiver in the digital processor. It is
this embedding, transmission, and decoding process that adds the vast majority of the
jitter to the digital data stream. One must go to monumental lengths to reduce jitter
introduced via the single-cable connection to acceptable levels.
Fortunately, it is quite a simple task to bypass the single-cable connection
altogether. One approach is to combine all of the various building blocks into an
integrated digital playback deck. The other method, used in the Ayre DDP, is to connect
the transport mechanism to the subsequent digital circuitry via a specialized
multi-conductor cable. This connection scheme allows for easy evaluation of different
digital transport mechanisms, in keeping with the underlying premise of the DDP.
The critical master clock is transmitted via balanced (differential) signals. Just as
with analog signals, balanced transmission confers distinct advantages by rejecting both
common-mode signals on the connecting cables, as well as any residual noise present on the
power supply rails.
The Digital Filter
The primary task of the digital filter is to move the image signals created by the
digitizing process to frequencies far beyond that of the reconstructed analog signal. This
is accomplished by resampling the stored digital data at some multiple (typically four or
eight) of the original sampling frequency. Resampling makes the task of the analog
anti-imaging filter much easier, allowing for a simpler, higher-performance analog filter
after the D/A chips. In addition, the digital filter may perform other tasks, including
applying de-emphasis and adding dither.
Digital-to-Analog Converter
This key component determines the linearity of the overall system. Here, two D/A chips
are used per channel in a balanced configuration to provide maximum rejection of digital
noise and improved signal-to-noise ratio. The D/A chips are typically provided with two
pairs of power supply connections, one pair for the digital circuitry and one pair for the
analog circuitry. In the Ayre DDP, the analog supply is provided by discrete zero-feedback
FET regulators for maximum sonic performance.
Analog Circuitry
This is the heart of the Ayre DDP, and the main reason for its superlative sound
quality. A high quality ladder D/A chip has a current output rather than a voltage output.
This necessitates using a current-to-voltage (I-V) converter to feed the subsequent analog
circuitry. With only a handful of exceptions, competing designs perform this I-V
conversion with an IC op-amp.
Even the best ICs cannot attain the sonic performance level available from a
well-designed discrete circuit. (Please refer to the Ayre technical paper Why Not ICs? for more information on this topic.) In fact, much
of the blame for the so-called digital sound can be traced to the use of ICs at
this critical point in the signal path.
Ayre has developed a unique differential I-V converter using discrete FETs with zero
negative feedback. This circuit rejects common-mode noise and distortion right at its
input, and is ideally suited to respond to the stringent demands created by the ultra-fast
D/A chips. Power is again supplied by discrete zero-feedback FET regulators. The net
result is truly analog-like performance from digital sources.
Conclusion
The Ayre DDP represents a turning point in the evolution of digital audio products. The
insights gained from the Digital Development Platform will be applied to forthcoming
production models. Since Ayre is one of the pioneering leaders of 96 kHz, 24-bit digital
audio technology, these new units will naturally incorporate this high-resolution
capability. When Ayre's digital products are released in late 1998, performance beyond
today's state-of-the-art will be available at realistic prices.
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